Open Project
Open Project File Save VCD Open File (FS) Check Simulatable Save VCD (FS) Save VCD Local Save VCD Preview Print Preview Close |
Restart
Load VCD Waveforms Add All to Sim Queue Run Run For... Single Step Stop Add All Ports Add Port... Add Signal ... Report Design Set Design Close |
Set Max Sim Time
Set Sim Chunk Timing Set Wave Offset Show Annotation Show Timeline Show Title Show Notes Show Values Show Timing Parameters Show Full Names Force GND = 0 Debug Comments Close |
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Open Project Select Service: LOCAL Server Select Project: |
Specify Clock Set As Clock Period High Time Offset |
Open File Select File: |
Save File Select File: |
Open Project File Open file: |
New Signal Signal Name Initial Value std_logic std_logic_vector Limit 1 Limit 2 |
Manually Find Model Select File: |
Constraint Editor Constraint Name: Description: Trigger Event: Constrained Event Occurs Sometimes Occurs Always Occurs Never Min, Setup or Hold Time Display Time Max Time |
Constraint Editor |
Signal Selector Select a Signal: |
Design Selector Select a Top Design: |